The present invention relates to a voltage converter circuit and, more particularly, to a voltage converter circuit for converting a binary signal to a higher-voltage binary signal.
In a nonvolatile semiconductor memory comprising MOS transistors as memory cells each having a floating gate, a voltage higher than a normal data read voltage is used to write data. For example, the data read voltage is +5 V, the data write voltage is about +20 V.
The data write signal is obtained by voltage-converting the read signal.
FIG. 1 shows a circuit which is obtained by modifying a circuit of FIG. 4 in "ISSCC DIGEST OF TECHNICAL PAPERS", Febuary 1982, p. 183 so as to obtain a higher-voltage binary signal. The word "higher-voltage binary signal" means a signal in which a voltage corresponding to logic "0" is the same as that corresponding to logic "0" of the input binary signal and a voltage corresponding to logic "1" is higher than that corresponding to logic "1" of the input binary signal. In this example, a voltage corresponding to logic "1" of the input binary signal is set at e.g., 5 V, a voltage corresponding to logic "1" of the higher-voltage binary signal is set at e.g., 21 V, and a voltage corresponding to logic "0" is commonly set at e.g., 0 V for the input binary signal and the higher-voltage binary signal.
Referring to FIG. 1, a voltage Vcc is a power supply voltage for data read and is set at a voltage of +5 V. A voltage Vpp is a power supply voltage for data write and is set at +21 V. As shown in FIG. 1, a binary signal S is supplied to an inverter 11 to which the power supply voltage Vcc is supplied. When the binary signal S is set at logic "0" (ground level, i.e., 0 V), its inverted signal S is set at logic "1" (voltage Vcc).
The signal S is supplied to the source of an n-channel MOS transistor 12 having a gate to which the power supply voltage Vcc is normally applied. A circuit point 13 to which the drain of the MOS transistor 12 is connected is set at a voltage (Vcc-Vth) obtained by subtracting a threshold voltage Vth of the MOS transistor 12 from the power supply voltage Vcc. The voltage at the circuit point 13 is applied to a CMOS inverter 16 which receives the power supply voltage Vpp and which comprises a p-channel MOS transistor 14 and an n-channel MOS transistor 15. If the threshold voltage of the CMOS inverter 16 is designed to be lower than the voltage (Vcc-Vth), a voltage at a voltage output terminal 17 connected to the output terminal of the CMOS inverter 16 decreases to 0 V. In this case, a p-channel MOS transistor 18 which is inserted between a terminal which is supplied with the power supply voltage Vpp and the circuit point 13 and which receives at its gate the voltage at the voltage output terminal 17 is turned on, so that the voltage at the circuit point 13 is increased. When the voltage at the circuit point 13 exceeds the voltage (Vcc-Vth), the transistor 12 is turned off and the voltage at the circuit point 13 increases to the voltage Vpp. The voltage Vpp is then applied to the gate of the p-channel MOS transistor 14 in the CMOS inverter 16, so that the p-channel MOS transistor 14 is turned off. As a result, the voltage at the voltage output terminal 17 comes close to 0 V.
In this state, the binary signal S goes to logic "1". The inverted output signal S from the inverter 11 goes to logic "0". The MOS transistor 12 is then turned on, so that the voltage at the circuit point 13 is decreased from the voltage Vpp. When the voltage at the circuit point 13 is decreased to be lower than the threshold voltage of the CMOS inverter 16, the output level of the inverter 16 is inverted, so that the voltage at the voltage output terminal 17 is increased toward the voltage Vpp. The current supply capacity of the MOS transistor 18 is decreased, and the voltage at the circuit point 13 is decreased. As a result, the voltage at the voltage output terminal 17 is finally stabilized at the voltage Vpp.
In order to instantaneously increase the voltage at the voltage output terminal 17 to the voltage Vpp, the voltage at the circuit point 13 must be instantaneously decreased. For this purpose, the conductance of the MOS transistor 12 must be sufficiently greater than that of the MOS transistor 18.
According to the circuit shown in FIG. 1, a higher-voltage binary signal can be obtained from the input binary signal S.
In the conventional circuit shown in FIG. 1, the voltage at the circuit point 13 is increased up to the voltage (Vcc-Vth) immediately after the binary signal S is inverted from logic "1" to logic "0". The driving capacity of the n-channel MOS transistor 15 is not sufficient as compared with the case wherein the power supply voltage Vcc is directly supplied to the gate thereof. As a result, time for setting the voltage at the voltage output terminal 17 to be 0 V becomes prolonged, resulting in inconvenience. This becomes significant when the conventional circuit is used under the condition where the power supply voltage Vcc is decreased. In addition to this disadvantage, the voltage at the voltage output terminal 17 is stabilized to be a given value and cannot be set to be completely 0 V if the power supply voltage Vcc is not properly set.
In order to instantaneously decrease the voltage at the circuit point 13 of the conventional circuit, the conductance ratio of the transistor 12 to the transistor 18 must be determined to be a predetermined value or higher. For this reason, the conventional circuit has many design and manufacturing limitations, resulting in inconvenience.